Manufacturing method of semiconductor device and semiconductor device

ABSTRACT

First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

CROSS-REFERENCE TO RELATED APPLICATION

This is a Continuation of U.S. patent application Ser. No. 17/060,486,filed Oct. 1, 2020, which is a Continuation of U.S. patent applicationSer. No. 16/282,981, filed on Feb. 22, 2019, now U.S. Pat. No.10,833,188, issued Nov. 10, 2020, which claims priority from JapanesePatent Application No. 2018-046411 filed on Mar. 14, 2018, the contentof each are hereby incorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a manufacturing method of asemiconductor device and the semiconductor device, and can be suitablyapplied in particular to a semiconductor device using silicon carbide(SiC).

BACKGROUND OF THE INVENTION

In the field of the semiconductor device having a transistor, asemiconductor device using an SiC substrate has been under study. Forexample, when an SiC substrate is used in a power transistor, breakdownvoltage increases because SiC has a wider bandgap than silicon (Si).

For example, Japanese Patent Application Laid-Open Publication No.2017-38001 (Patent Document 1) discloses a semiconductor device with anMIS structure using SiC. In this semiconductor device, a first region ofa p well region is inclined at an inclination angle θ.

Furthermore, Japanese Patent No. 5196980 (Patent Document 2) discloses asemiconductor device in which an impurity concentration of a lowermostportion of a semi-superjunction structure is made higher than that ofother portions in a p-type pillar layer, so that a depletion layer islikely to spread downward (into a drift layer) from a pn junctionbetween the lowermost portion and the drift layer, and thus a structurewith high breakdown voltage can be achieved.

SUMMARY OF THE INVENTION

The inventors are engaged in research and development of semiconductordevices using silicon carbide (SiC) and have made every effort toimprove characteristics of semiconductor devices.

As described above, SiC has a wider bandgap than silicon (Si) and thuscan increase breakdown voltage. However, in a MISFET that is asemiconductor device using SiC, an increasing breakdown voltage of SiCmay pose a problem to the breakdown voltage of a gate insulating film.That is, the gate insulating film may disadvantageously break beforebreakage of SiC occurs.

In this case, as described below, by disposing an electric-fieldrelaxation layer near a trench in which a gate electrode is embedded viathe gate insulating film, the electric field generated near the gateinsulating film is relaxed to thereby enhance the breakdown voltage ofthe gate insulating film.

However, in a case where the electric-field relaxation layer is formedby ion implantation or the like with using a predetermined film as amask, alignment margins are needed and miniaturization of elementscannot be achieved. Furthermore, possible mask misalignment hinders theelectric-field relaxation layers from being formed symmetrically withrespect to the trench, leading to degraded element characteristics.

Thus, there is a desire for study of a manufacturing method of asemiconductor device and a configuration of a semiconductor device thatallow miniaturization of the elements and improvement of the elementcharacteristics.

An outline of typical embodiments disclosed in the present applicationwill be given below in brief.

A manufacturing method of a semiconductor device illustrated in anembodiment disclosed in the present application includes the steps of:embedding a dummy gate in a trench; protruding the dummy gate from asource region; and forming side wall films on side walls of the dummygate. The manufacturing method further includes the step ofion-implanting impurities of a conductivity type opposite to aconductivity type of a drift layer with using the dummy gate and theside wall film as a mask, thereby forming a first semiconductor regionin the drift layer on a first side of the trench and forming a secondsemiconductor region in the drift layer on a second side of the trench.

A semiconductor device illustrated in an embodiment disclosed in thepresent application includes an SiC layer having a drift layer, achannel layer on the drift layer, and a source region on the channellayer. Also, the semiconductor device further includes: a trenchpenetrating the channel layer to reach the drift layer to be in contactwith the source layer; a gate insulating film formed on an inner wall ofthe trench; a gate electrode embedded in the trench; a firstsemiconductor region formed in the drift layer on a first side of thetrench; and a second semiconductor region formed in the drift layer on asecond side of the trench. In addition, a distance between the trenchand the first semiconductor region and a distance between the trench andthe second semiconductor region are each shorter than or equal to awidth of the trench.

According to the manufacturing method of the semiconductor deviceillustrated in the typical embodiments disclosed below in the presentapplication, it is possible to manufacture a semiconductor devicecapable of achieving miniaturization of elements and favorable elementcharacteristics. Furthermore, according to the semiconductor deviceillustrated in the typical embodiments disclosed below in the presentapplication, it is possible to provide a fine semiconductor device withfavorable characteristics.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a configuration of asemiconductor device according to a first embodiment;

FIGS. 2A and 2B are cross-sectional views each illustrating amanufacturing process of the semiconductor device according to the firstembodiment;

FIGS. 3A and 3B are cross-sectional views each illustrating amanufacturing process of a semiconductor device in the comparativeexample;

FIG. 4 is a cross-sectional view illustrating the manufacturing processof the semiconductor device in the comparative example;

FIG. 5 is a cross-sectional view illustrating the manufacturing processof the semiconductor device in the comparative example;

FIGS. 6A and 6B are plan views each illustrating a configuration of thesemiconductor device according to the first embodiment;

FIG. 7 is a cross-sectional view illustrating an example of a peripheralconfiguration of the semiconductor device according to the firstembodiment;

FIG. 8 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 9 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 10 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 11 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 12 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 13 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 14 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 15 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 16 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 17 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 18 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 19 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 20 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 21 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the first embodiment;

FIG. 22 is a graph illustrating a relationship between an impurityconcentration in a drift layer and an interval between a trench and ap-type semiconductor region;

FIG. 23 is a cross-sectional view illustrating a semiconductor device inwhich the impurity concentration of the drift layer is increased;

FIG. 24 is a cross-sectional view illustrating a configuration of asemiconductor device in Applied Example 1 of a second embodiment;

FIG. 25 is a cross-sectional view illustrating a configuration of asemiconductor device in Applied Example 2 of the second embodiment;

FIG. 26 is a cross-sectional view illustrating a configuration of asemiconductor device according to a third embodiment;

FIG. 27 is a cross-sectional view illustrating a manufacturing processof the semiconductor device according to the third embodiment;

FIG. 28 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 29 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 30 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 31 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 32 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 33 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 34 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 35 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 36 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 37 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 38 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the third embodiment;

FIG. 39 is a cross-sectional view illustrating a configuration of asemiconductor device according to a fourth embodiment;

FIG. 40 is a cross-sectional view illustrating a manufacturing processof the semiconductor device according to the fourth embodiment;

FIG. 41 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fourth embodiment;

FIG. 42 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fourth embodiment;

FIG. 43 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fourth embodiment;

FIG. 44 is a cross-sectional view illustrating a configuration of asemiconductor device according to a fifth embodiment;

FIG. 45 is a cross-sectional view illustrating a manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 46 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 47 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 48 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 49 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 50 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 51 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 52 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 53 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the fifth embodiment;

FIG. 54 is a cross-sectional view illustrating a configuration of asemiconductor device according to a sixth embodiment;

FIG. 55 is a cross-sectional view illustrating a manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 56 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 57 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 58 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 59 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 60 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 61 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 62 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 63 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment;

FIG. 64 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment; and

FIG. 65 is a cross-sectional view illustrating the manufacturing processof the semiconductor device according to the sixth embodiment.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the entireor a part of the other as a modification example, details, or asupplementary explanation thereof. Also, in the embodiments describedbelow, when mentioning the number of elements (including number ofpieces, values, amount, range, and the like), the number of the elementsis not limited to a specific number unless otherwise stated or exceptthe case where the number is apparently limited to a specific number inprinciple, and the number larger or smaller than the specified number isalso applicable.

Further, in the embodiments described below, it goes without saying thatthe components (including element steps) are not always indispensableunless otherwise stated or except the case where the components areapparently indispensable in principle. Similarly, in the embodimentsdescribed below, when the shape of the components, positional relationthereof, and the like are mentioned, the substantially approximate andsimilar shapes and the like are included therein unless otherwise statedor except the case where it is conceivable that they are apparentlyexcluded in principle. The same goes for the number and the likedescribed above (including the number of pieces, numerical value,amount, range and others).

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference charactersthroughout the drawings for describing the embodiments, and therepetitive description thereof will be omitted. Also, when a pluralityof similar members (portions) are present, an individual or specificportion among them is denoted by a generic character added with a symbolin some cases. In addition, the description of the same or similarportions is not repeated in principle unless particularly required inthe following embodiments.

Also, in some drawings used in the following embodiments, hatching isomitted even in a cross-sectional view so as to make the drawings easyto see. In addition, hatching is used even in a plan view so as to makethe drawings easy to see.

Further, the size of respective portions does not correspond to that ofan actual device in cross-sectional view and plan view, and a specificportion may be shown in a relatively enlarged manner in some cases so asto make the drawings easy to see. Also, even when a cross-sectional viewand a plan view correspond to each other, a specific portion may beshown in a relatively enlarged manner in some case so as to make thedrawings easy to see.

First Embodiment

[Description of Structure]

A semiconductor device according to a first embodiment will be describedbelow in detail with reference to the drawings.

FIG. 1 is a cross-sectional view illustrating a configuration of asemiconductor device according to the first embodiment. FIGS. 2A and 2Bare cross-sectional views each illustrating a manufacturing process ofthe semiconductor device according to the first embodiment. Thesemiconductor device illustrated in FIG. 1 is a trench gate powertransistor.

As illustrated in FIG. 1 , the semiconductor device according to thefirst embodiment includes a drift layer (drain region) DR provided on afront surface (first surface) side of an SiC substrate 1S, a channellayer CH provided on the drift layer DR, and a source region SR providedon the channel layer CH. The drift layer DR includes an n-typesemiconductor region, the channel layer CH includes a p-typesemiconductor region, and the source region SR includes an n-typesemiconductor region. The semiconductor regions are formed of SiC, thep-type semiconductor region includes p-type impurities, and the n-typesemiconductor region includes n-type impurities. Furthermore, thesemiconductor regions are formed in, for example, an epitaxial layer EPmade of SiC.

Also, the semiconductor device according to the first embodimentincludes a gate electrode GE arranged, via a gate insulating film GI, ina trench TR penetrating the source region SR and the channel layer CH toreach the drift layer DR.

Furthermore, on each of the right and left sides of the trench TR, oneend of the source region SR is in contact with the trench TR, and a bodycontact region BC is provided at the other end of the source region SRopposite to the one end. The body contact region BC includes a p-typesemiconductor region having a higher impurity concentration than thechannel layer CH and is formed to achieve ohmic contact with the channellayer CH.

Furthermore, an interlayer insulating film IL1 is provided on the gateelectrode GE. The interlayer insulating film IL1 is formed of aninsulating film such as a silicon oxide film. A source electrode SE isprovided on the interlayer insulating film IL1 and in a contact hole C1in the interlayer insulating film IL1. The source electrode SE is formedof a conductive film. Note that a portion of the source electrode SElocated inside the contact hole C1 may be regarded as a plug (via), anda portion of the source electrode SE extending on the interlayerinsulating film IL1 may be regarded as a wiring. The source electrode SEis electrically connected to the body contact regions BC and the sourceregion SR. A surface protection film PAS made of an insulating film isformed on the source electrode SE. Note that a drain electrode DE isformed on a back surface (second surface) side of the SiC substrate 1S.

The transistor illustrated in FIG. 1 is repeatedly arranged in plan viewas described later (see FIG. 6B). Thus, the transistor illustrated inFIG. 1 may be referred to as a “unit transistor (unit cell) UC”. The“unit transistor (unit cell) UC” is a minimum repetition unit.

In the first embodiment, p-type semiconductor regions (PRa and PRb orelectric-field relaxation layers) that are embedded layers are providedbelow the channel layer CH on both sides of the trench TR. The p-typesemiconductor regions (PRa and PRb) are located below the channel layerCH and include impurities of a conductivity type opposite to theconductivity type of the drift layer DR (p-type impurities). Byproviding the p-type semiconductor regions (PRa and PRb) as describedabove, the breakdown voltage of the gate insulating film GI, forexample, the bottom electric field in the trench described later can beimproved.

As illustrated in FIG. 2A and FIG. 2B, the p-type semiconductor regions(PRa and PRb or electric-field relaxation layers) are formed by ionimplantation using a dummy gate DG provided in the trench TR to protrudeupward from the trench TR and side wall films SW formed on both sides ofthe dummy gate DG as a mask. That is, the p-type semiconductor regions(PRa and PRb or electric-field relaxation layers) are impurity regionsformed in a self-alignment manner in association with the side walls ofthe side wall films SW of the dummy gate DG. This enables a reduction ina distance La between the p-type semiconductor region PRa and the trenchTR (the shortest distance in plan view, see FIG. 6B) and a distance Lbbetween the p-type semiconductor region PRb and the trench TR (theshortest distance in plan view). Each of the distances La and Lbcorresponds to a width of a corresponding one of the side wall films SW(a length in an X direction). Furthermore, the distance La and thedistance Lb can be made approximately equivalent to each other. In otherwords, it is possible to reduce a difference between the distance La andthe distance Lb. Moreover, in other words, variations in the distance Laand the distance Lb can be reduced. The distance La and distance Lb thusreduced allow semiconductor elements (unit transistors UC) to beminiaturized. Furthermore, when the distance La and the distance Lb areset approximately equivalent to each other to enhance symmetry of thetwo semiconductor regions (PRa and PRb) with respect to the trench TR,element characteristics can be improved.

In contrast, in a semiconductor device in a comparative exampleillustrated below, a distance L2 a and a distance L2 b are increased dueto mask alignment margins when forming the p-type semiconductor regions(PRa and PRb), and possible mask misalignment may make the distance L2 aand the distance L2 b unbalanced.

FIGS. 3A to 5 are cross-sectional views illustrating a manufacturingprocess of the semiconductor device in the comparative example. Thesemiconductor device in the comparative example can be formed asfollows. First, the SiC substrate 1S in which the drift layer DR, thechannel layer CH, and the source region SR are formed in this order frombottom to top and the body contact region BC is formed in a stackedportion of the source region SR and the channel layer CH is prepared.Then, as illustrated in FIG. 3A, p-type impurities are ion-implantedwith using a hard mask HM1 as a mask to form the p-type semiconductorregions (PRa and PRb). The p-type semiconductor regions (PRa and PRb)are formed on both sides of a region where the trench is to be formed.Next, after the hard mask HM1 is removed, as illustrated in FIG. 3B, thesource region SR, the channel layer CH, and the drift layer DR arepartially removed with using a hard mask HM2 as a mask to form thetrench TR such that the trench TR is located between the p-typesemiconductor regions PRa and PRb. Thereafter, the hard mask HM2 isremoved.

In the manufacturing process in the comparative example described above,alignment margins for the hard mask HM1 for forming the p-typesemiconductor regions (PRa and PRb) are added, and this makes thereduction in the distance between the p-type semiconductor regions PRaand PRb difficult. For example, it is difficult to set each of thedistance L1 a and the distance L1 b shorter than or equal to the width Wof the trench TR, which is formed to have a width close to a resolutionlimit.

Furthermore, since the p-type semiconductor regions (PRa and PRb) areformed and then the trench TR is formed so as to be located between thep-type semiconductor regions PRa and PRb, possible misalignment of thehard mask for forming the trench TR (mask misalignment) makes thedistance L2 a and the distance L2 a unbalanced as illustrated in, forexample, FIG. 4 and FIG. 5 (in this case, L2 a>L2 b). Such unbalancebetween the distance L2 a and the distance L2 b degrades thecharacteristics of semiconductor elements.

That is, in a region with the short distance L2 b, the distance betweenthe trench (gate electrode GE) TR and the electric-field relaxationlayer (p-type semiconductor region PRb) is short, so that anelectric-field relaxation effect is increased. However, a current pathis narrowed to increase on-resistance. On the other hand, in a regionwith the long distance L2 a, the distance between the trench (gateelectrode GE) TR and the electric-field relaxation layer (p-typesemiconductor region PRb) is long, so that an appropriate current pathcan be ensured to inhibit an increase in the on-resistance. However, theelectric-field relaxation effect is reduced. As described above, theon-resistance and the electric-field relaxation effect, which are in atrade-off relationship, are unbalanced between the right and left of thetrench (gate electrode GE) TR, resulting in that the on-resistanceincreases and the electric-field relaxation effect decreases in terms ofthe semiconductor elements.

In contrast, according to the first embodiment, the p-type semiconductorregions (PRa and PRb or electric-field relaxation layers) are formed ina self-alignment manner by ion implantation using the dummy gate DG inthe trench TR and the side wall films SW formed on both sides of thedummy gate DG as a mask as described above. This enables a reduction inthe distance La between the p-type semiconductor region PRa and thetrench TR and the distance Lb between the p-type semiconductor regionPRb and the trench TR. Furthermore, the symmetry of the semiconductorregions with respect to the trench can be enhanced. That is, thedistance between the p-type semiconductor regions PRa and PRb can bereduced, and each of the distance La and the distance Lb can be madeshorter than or equal to the width W of the trench TR, which is formedto have a width close to the resolution limit. The width close to theresolution limit is, for example, 1 μm or less. This allows thesemiconductor elements to be miniaturized, and the semiconductorelements can be highly integrated in the semiconductor device.

Furthermore, the on-resistance and the electric-field relaxation effect,which are in a trade-off relationship, are balanced between the rightand left of the trench (gate electrode GE) TR, so that the on-resistanceand the electric-field relaxation effect set in a design phase can beobtained. As described above, it is possible to improve thecharacteristics of the semiconductor elements.

FIGS. 6A and 6B are plan views each illustrating a configuration of thesemiconductor device according to the first embodiment. The region UCillustrated in FIG. 1 corresponds to, for example, the region UCillustrated in FIG. 6A, and FIG. 1 corresponds to a cross section takenalong line A-A in FIG. 6B.

As illustrated in FIG. 6B, the gate electrode GE is planarly shaped likea rectangle with long sides in a Y direction. The trench TR is planarlyshaped like a rectangle with long sides in the Y direction. The sourceregion SR is arranged on both sides of the trench TR. The source regionSR is planarly shaped like a rectangle with long sides in the Ydirection. Each of the body contact regions BC is arranged outside thesource region SR. The body contact region BC is planarly shaped like arectangle with long sides in the Y direction.

As described above, like the trench TR and the gate electrode GE, thep-type semiconductor regions (PRa and PRb) extend in the Y direction(the direction perpendicular to the page of FIG. 1 ). As illustrated inFIG. 6B, the p-type semiconductor regions PRa and PRb are arranged at apredetermined interval from each other. The unit transistors UC arerepeatedly arranged in the X direction.

The source electrode SE is arranged to extend over the gate electrode GEas illustrated in FIG. 1 and FIG. 6A. FIG. 7 is a cross-sectional viewillustrating an example of a peripheral configuration of thesemiconductor device according to the first embodiment, and correspondsto a cross section taken along line B-B in FIG. 6A. Furthermore,although not illustrated in the cross section in FIG. 1 , a gate line GLand a gate pad GPD that are connected to the gate electrode GE areprovided (see FIG. 6A and FIG. 7 ). The gate line GL and the gate padGPD can be formed of a conductive film in the same layer as that of thesource electrode SE. Furthermore, although not illustrated in the crosssection in FIG. 1 , a source line SL that is connected to the sourceelectrode SE is provided (see FIG. 6A and FIG. 7 ). The source line SLcan be formed of a conductive film in the same layer as that of thesource electrode SE. PRt represents a semiconductor region formed in thesame layer as that of the p-type semiconductor regions (PRa and PRb),BCt represents a semiconductor region formed in the same layer as thatof the body contact region BC, and CHt represents a semiconductor regionformed in the same layer as that of the channel layer CH. Furthermore,TM represents a p-type semiconductor region provided around an outerperiphery of a cell region CR. Note that the peripheral configurationillustrated in FIG. 7 is just an example and another configuration maybe used.

<Operation>

In the semiconductor device (transistor) according to the firstembodiment, when a gate voltage higher than or equal to a thresholdvoltage is applied to the gate electrode GE, an inversion layer (n-typesemiconductor region) is formed in the channel layer (p-typesemiconductor region) CH that is in contact with side surfaces of thetrench TR. Thus, the source region SR and the drift layer DR areelectrically connected by the inversion layer, and when a potentialdifference is present between the source region SR and the drift layerDR, electrons flow from the source region SR through the inversion layerto the drift layer DR. In other words, a current flows from the driftlayer DR through the inversion layer to the source region SR. Thetransistor can be turned on in this manner.

On the other hand, when a voltage lower than the threshold voltage isapplied to the gate electrode GE, the inversion layer formed in thechannel layer CH disappears, making the source region SR and the driftlayer DR electrically discontinuous. The transistor can be turned off inthis manner.

As described above, the ON/OFF operation of the transistor is performedby changing the gate voltage applied to the gate electrode GE of thetransistor.

[Description of Manufacturing Method]

Next, a manufacturing method of the semiconductor device according tothe first embodiment will be described with reference to FIGS. 8 to 21 ,and a configuration of the semiconductor device will be furtherclarified. FIGS. 8 to 21 are cross-sectional views illustrating amanufacturing process of the semiconductor device according to the firstembodiment.

First, as illustrated in FIG. 8 , the SiC substrate (a semiconductorsubstrate or a wafer made of SiC) 1S on which the epitaxial layer EPmade of SiC is formed is prepared.

A method of forming the epitaxial layer EP on the SiC substrate 1S isnot limited, but the epitaxial layer EP can be formed as follows. Forexample, an n-type epitaxial layer made of SiC is grown on the SiCsubstrate 1S while introducing n-type impurities such as nitrogen (N) orphosphorus (P), thereby forming the epitaxial layer EP. The drift layerDR is provided below the epitaxial layer EP.

Then, as illustrated in FIG. 9 , a p-type semiconductor region servingas the channel layer CH and an n-type semiconductor region serving asthe source region SR are formed by ion implantation. Furthermore, p-typesemiconductor regions serving as the body contact regions BC are formedby ion implantation. For example, p-type impurities (aluminum (Al),boron (B), or the like) are ion-implanted into an upper portion of theepitaxial layer EP to form the p-type semiconductor region (channellayer CH), and n-type impurities (nitrogen (N), phosphorus (P), or thelike) are subsequently ion-implanted into an upper portion of the p-typesemiconductor region (channel layer CH) to form the n-type semiconductorregion (source region SR). The concentration of the n-type impurities inthe source region SR is higher than the concentration of the p-typeimpurities in the epitaxial layer (drift layer DR) EP. Next, p-typeimpurities are selectively ion-implanted into a stacked portion of thep-type semiconductor region (channel layer CH) and the n-typesemiconductor region (source region SR) to form the p-type semiconductorregions (body contact regions BC). The concentration of the p-typeimpurities in the body contact regions BC is higher than theconcentration of the p-type impurities in the channel layer CH. In theion implantation step, the impurities are ion-implanted with using aphotoresist film or a hard mask as a mask. Furthermore, in the ionimplantation step, the impurity concentration, an implantation depth ofthe impurities, and the like can be accurately controlled by using themulti-stage ion implantation. The multi-stage ion implantation is amethod of performing ion implantation a plurality of times for eachpredetermined depth while adjusting the implantation energy and theimpurity concentration.

Then, as illustrated in FIG. 10 , the trench TR that penetrates thesource region SR and the channel layer CH to reach the drift layer DR isformed.

For example, an insulating film (for example, a plasma TEOS film with afilm thickness of approximately 4 μm) IF1 having an opening in aformation region of the trench TR is formed on the epitaxial layer EP byusing a photolithography technique and an etching technique. Next, thesource region SR, the channel layer CH, and an upper portion of thedrift layer DR are etched with using the insulating film (hard mask) IF1as a mask to form the trench TR with a width of approximately 0.8 μm anda depth of approximately 1.5 μm. The drift layer DR, the channel layerCH, the source region SR, and the insulating film IF1 are exposed to theside surfaces of the trench TR in this order from bottom to top.Furthermore, the drift layer DR is exposed to a bottom surface of thetrench TR.

Then, as illustrated in FIGS. 11 to 13 , the dummy gate DG that isprovided in the trench TR and protrudes upward from the trench TR isformed. First, as illustrated in FIG. 11 , a polycrystalline siliconfilm PS is deposited as a dummy gate material in the trench TR and onthe insulating film IF1 so as to have a film thickness sufficient tofill the trench TR (for example, a film thickness of approximately 1 μm)by chemical vapor deposition (CVD) or the like. Then, as illustrated inFIG. 12 , an upper portion of the polycrystalline silicon film PS ispolished by chemical mechanical polishing (CMP) or the like until theinsulating film IF1 is exposed. The dummy gate DG is formed in thismanner. The polishing by the CMP may be replaced with etch-back. Next,as illustrated in FIG. 13 , the insulating film IF1 is removed by theetching technique. For example, wet etching using diluted HF isperformed. As a result, the dummy gate DG that is embedded in the trenchTR and protrudes from a front surface of the epitaxial layer (sourceregion SR) EP by a distance equivalent to the film thickness of theinsulating film IF1 can be formed. A height H of a portion (protrudingportion) of the dummy gate DG that protrudes from the front surface ofthe epitaxial layer (source region SR) EP is at least 1.5 times, morepreferably, at least 1.8 times as large as a depth D of the trench TR.By ensuring the height of the protruding portion as described above,control of a width (a length in the X direction) of each of the sidewall films SW described below can be facilitated.

Next, as illustrated in FIGS. 14 to 16 , the p-type semiconductorregions (PRa and PRb) are formed in the drift layer DR on both sides ofthe trench TR. First, as illustrated in FIG. 14 , an insulating film(for example, a silicon oxide film) IF2 for forming the side wall filmsSW is formed on the epitaxial layer (source region SR) EP and on thedummy gate DG by using CVD or the like. Then, the insulating film IF2 isetched back as illustrated in FIG. 15 . In the etch-back step, theinsulating film IF2 is removed by anisotropic dry etching from a frontsurface thereof by a predetermined film thickness. This step allows theinsulating film IF2 to remain like side walls on the side wall portionson both sides of the protruding portion of the dummy gate DG to form theside wall films SW. The width (the length in the X direction) of each ofthe side wall films SW can be controlled by the film thickness of theinsulating film IF2 and etch-back conditions.

In this case, over-etching may be performed to slightly etch the frontsurface of the epitaxial layer (source region SR) EP on both sides ofthe side wall films SW. In this case, a step difference is generatedbetween the front surface of the epitaxial layer (source region SR) EPcovered with the side wall films SW and the front surface of theepitaxial layer (source region SR) EP located outside the side wallfilms SW. By slightly etching the front surface of the epitaxial layer(source region SR) EP as described above, front surface portions of theepitaxial layer (source region SR) EP in which the n-type impurities arelikely to have a low concentration can be removed, and connectionresistance between the source electrode SE and the source region SR oreach of the body contact regions BC described later can be reduced. Inparticular, when the source region SR and the body contact regions BCare formed by ion implantation, a concentration gradient of the impurityions is likely to occur, and the diffusion (uniformization) of theimpurities by thermal treatment is less likely to be achieved in the SiClayer (the epitaxial layer made of SiC). Thus, the effect of reductionin the connection resistance between the source electrode SE and thesource region SR obtained by slightly etching the front surface of theepitaxial layer (source region SR) EP is great.

Next, as illustrated in FIG. 16 , the p-type semiconductor regions (PRaand PRb) are formed by ion implantation. For example, p-type impuritiessuch as aluminum (Al) or boron (B) are implanted into the drift layer DRwith using the dummy gate DG and the side wall films SW as a mask.During the ion implantation, ion implantation conditions such as ionimplantation energy are adjusted such that each of the p-typesemiconductor regions (PRa and PRb) is located at the position deeperthan the lower surface of the channel layer CH. The above-describedmulti-stage implantation may be used to form the p-type semiconductorregions (PRa and PRb).

The p-type semiconductor regions (PRa and PRb) preferably extend to aposition deeper than a lower end of the trench TR. In this case, anupper surface of each of the p-type semiconductor regions (PRa and PRb)is located at a position higher than the bottom surface of the trenchTR. Furthermore, a lower surface of each of the p-type semiconductorregions (PRa and PRb) is located at a position lower than the bottomsurface of the trench TR. In other words, the trench TR and the p-typesemiconductor regions (PRa and PRb) are arranged at overlappingpositions in a depth direction (Z direction).

Also, in this step, the p-type semiconductor regions (PRa and PRb orelectric-field relaxation layers) are formed by ion implantation usingthe dummy gate DG in the trench TR and the side wall films SW formed onboth sides of the dummy gate DG as a mask as described above. Therefore,it is possible to reduce the distance La between the p-typesemiconductor region PRa and the trench TR and the distance Lb betweenthe p-type semiconductor region PRb and the trench TR. Furthermore, thesymmetry of the semiconductor regions with respect to the trench can beenhanced. That is, the distance between the p-type semiconductor regionsPRa and PRb can be reduced, and for example, each of the distance La andthe distance Lb can be made shorter than or equal to the width W of thetrench TR, which is formed to have a width close to the resolutionlimit.

Then, as illustrated in FIG. 17 , the dummy gate DG and the side wallfilms SW are removed by the etching technique. For example, the sidewall films SW are removed by wet etching using diluted HF, and the dummygate DG is removed by wet etching using nitric-hydrofluoric acid.

In the above-described step, the polycrystalline silicon film PS is usedas a dummy gate material. However, another material exhibitingappropriate etching selectivity with respect to the insulating film IF2may be used when the side wall films SW are formed. The expression“exhibit appropriate etching selectivity” means the condition in which asufficient difference in etching rate is present between the films (theinsulating film IF2 and the dummy gate DG) in the etching step. When theside wall films SW are formed, the etching rate of the dummy gate DG islower than the etching rate of the insulating film IF2. For example, Si,N, W, or Al may be used as the dummy gate material other thanpolycrystalline silicon.

Then, thermal treatment (activation annealing) is performed to activatethe already implanted impurities. For example, thermal treatment isperformed at 1700° C. At this time, a protection film made of amorphouscarbon may be formed on the SiC substrate 1S for thermal treatment.

Then, as illustrated in FIG. 18 , a silicon oxide film as the gateinsulating film GI is formed on, for example, an inner wall of thetrench TR, the source region SR, and the body contact regions BC byatomic layer deposition (ALD) or the like. The epitaxial layer EPexposed in the trench TR may be subjected to thermal oxidation orthermal oxinitridation to form the gate insulating film GI. Furthermore,a high-dielectric-constant film such as an aluminum oxide film or ahafnium oxide film which has a higher dielectric constant than a siliconoxide film may be used as the gate insulating film GI other than asilicon oxide film or a silicon oxynitride film.

Then, the gate electrode GE which is arranged on the gate insulatingfilm GI and with which the trench TR is to be filled is formed. Forexample, a polycrystalline silicon film is deposited as a conductivefilm for forming the gate electrode GE by CVD or the like. Next, aphotoresist film (not illustrated in the drawings) covering a formationregion of the gate electrode GE is formed on the conductive film, andthe conductive film is etched with using the photoresist film as a mask.The gate electrode GE is formed in this manner.

Then, as illustrated in FIG. 19 , the interlayer insulating film IL1covering the gate electrode GE is formed, and the contact holes C1 areformed.

For example, a silicon oxide film is deposited as the interlayerinsulating film IL1 on the gate insulating film GI and the gateelectrode GE by the CVD. Then, a photoresist film (not illustrated inthe drawings) having openings above each of the body contact regions BCand portions of the source region SR on both sides of the body contactregions BC is formed on the interlayer insulating film IL1. Then, theinterlayer insulating film IL1 and the gate insulating film GI locatedbelow the interlayer insulating film IL1 are etched with using thephotoresist film as a mask, thereby forming the contact holes C1. Thebody contact region BC and the portions of the source region SR on bothsides of the body contact region BC are exposed on a bottom surface ofthe corresponding contact hole C1. Also, the interlayer insulating filmIL1 on the gate electrode GE, which is not illustrated in the crosssection in FIG. 19 , is removed to form a contact hole (not illustratedin the drawings) on the gate electrode GE.

Then, as illustrated in FIG. 20 , the source electrode SE is formed. Forexample, a TiN film is formed as a barrier metal film (not illustratedin the drawings) in each of the contact holes C1 and on the interlayerinsulating film IL1 by sputtering or the like. Next, an AlSi film isformed as a conductive film on the barrier metal film (not illustratedin the drawings) by sputtering or the like. The stacked film of thebarrier metal film (not illustrated in the drawings) and the conductivefilm (Al film) is then patterned to form the source electrode SE. Atthis time, the gate line GL and the gate pad GPD not illustrated in thecross section in FIG. 20 are formed (see FIG. 6A and FIG. 7 ). Thesource electrode SE and the like may be formed after a silicide film isformed on the bottom surface of each of the contact holes C1.

Next, as illustrated in FIG. 21 , the surface protection film PAS isformed to cover the source electrode SE, the gate line GL, and the gatepad GPD. For example, a silicon oxide film is deposited as the surfaceprotection film PAS on the source electrode SE and the like by the CVDor the like. Then, the surface protection film PAS is patterned toexpose a partial region (source pad SPD) of the source electrode SE anda partial region of the gate pad GPD. These exposed portions formexternal connection regions (pads).

Next, the SiC substrate 1S is placed such that a back surface (secondsurface) of the SiC substrate 1S opposite to a main surface of the SiCsubstrate 1S faces upward, and the back surface of the SiC substrate 1Sis ground to thin the SiC substrate 1S.

Next, the drain electrode DE is formed on the back surface of the SiCsubstrate 1S (FIG. 1 ). For example, the SiC substrate 1S is placed suchthat the back surface of the SiC substrate 1S faces upward, and a metalfilm is formed on the back surface side of the SiC substrate 1S. Forexample, a Ti film, an Ni film, and an Au film are sequentially formedby sputtering. In this manner, the drain electrode DE made of a metalfilm can be formed. Note that a silicide film may be formed between themetal film and the SiC substrate 1S. Thereafter, the SiC substrate(wafer) 1S including a plurality of chip regions is cut into therespective chip regions.

Through the steps described above, the semiconductor device according tothe first embodiment can be formed.

As described above, since the p-type semiconductor regions (PRa and PRbor electric-field relaxation layers) are formed by ion implantationusing the dummy gate DG in the trench and the side wall films SW formedon both sides of the dummy gate DG as a mask in the first embodiment, itis possible to reduce the distance La between the p-type semiconductorregion PRa and the trench TR and the distance Lb between the p-typesemiconductor region PRb and the trench TR. This enables thesemiconductor elements to be miniaturized, and the semiconductorelements can be highly integrated in the semiconductor device.

Furthermore, since the symmetry of the p-type semiconductor regions PRaand PRb with respect to the trench can be enhanced, the on-resistanceand the electric-field relaxation effect, which are in a trade-offrelationship, are balanced, so that the on-resistance and theelectric-field relaxation effect set in a design phase can be obtained.As described above, it is possible to improve the characteristics of thesemiconductor elements.

Moreover, since the distance La between the p-type semiconductor regionPRa and the trench TR and the distance Lb between the p-typesemiconductor region PRb and the trench TR can be reduced in the firstembodiment, the on-resistance can be reduced by improving the impurityconcentration of the drift layer (epitaxial layer EP) DR.

FIG. 22 is a graph illustrating a relationship between the intervalbetween the trench TR and the p-type semiconductor region PR (the TR-PRinterval or the distance La or Lb) and the impurity concentration of thedrift layer (epitaxial layer EP) DR. The horizontal axis represents theinterval between the trench TR and the p-type semiconductor region PR(distance La or Lb (μm)). Furthermore, the left vertical axis representsthe on-resistance (characteristic on-resistance Rsp (a.u.)) and theright vertical axis represents a bottom electric field in the trench(the bottom electric field at the maximum voltage (a.u.)).

FIG. 23 is a cross-sectional view of the semiconductor device in whichthe impurity concentration of the drift layer DR has been increased.Here, the case where the state of the n-type impurities in the driftlayer DR is changed from a low concentration (for example, 1E16 cm⁻³(1×10¹⁶ cm⁻³)) to a high concentration (for example, 2E16 cm⁻³ (2×10¹⁶cm⁻³)) will be studied.

As illustrated in FIG. 22 , in a case where the interval (distance La orLb) between the trench TR and the p-type semiconductor region PR isreduced from 1.2 μm to 0.6 μm and the concentration of the n-typeimpurities in the drift layer DR is changed from 1E16 cm⁻³ to 2E16 cm⁻³,the on-resistance can be reduced (arrow a). Furthermore, even though thebottom electric field in the trench is increased, the bottom electricfield can be kept approximately at Emax (an allowable value for a casewhere the interval is 1.2 μm and the n-type impurities in the driftlayer DR have low concentration).

As described above, by adjusting the impurity concentration of the driftlayer (epitaxial layer EP) DR, the on-resistance can be reduced withoutchanging the bottom electric field in the trench. That is, theon-resistance can be improved while achieving the electric-fieldrelaxation effect, which is in a trade-off relationship with theon-resistance.

Second Embodiment

In a second embodiment, an applied example of the first embodiment willbe described.

Applied Example 1

FIG. 24 is a cross-sectional view illustrating a configuration of asemiconductor device in Applied Example 1 of the second embodiment.

In the first embodiment (FIG. 1 ), a bottom surface of each of the bodycontact regions BC is located at a position higher than the uppersurface of the p-type semiconductor regions PRa and PRb. However, thebottom surface of the body contact region BC may be located at aposition lower than the upper surface of the p-type semiconductorregions PRa and PRb.

For example, as illustrated in FIG. 24 , the body contact regions BC areformed deeply such that a lower portion of each of the body contactregions BC overlaps an upper portion of the corresponding one of thep-type semiconductor regions PRa and PRb. Such deep body contact regionsBC can be formed by, for example, adding a deeper ion implantation stepto the multi-stage ion implantation step.

Applied Example 2

FIG. 25 is a cross-sectional view illustrating a configuration of asemiconductor device in Applied Example 2 of the second embodiment.

In the first embodiment (FIG. 1 ), the upper surface of each of thep-type semiconductor regions PRa and PRb is located at a position lowerthan an upper surface of the channel layer CH. However, the uppersurface of each of the p-type semiconductor regions PRa and PRb may belocated at approximately the same position as that of the upper surfaceof the channel layer CH. In Applied Example 2, each of the p-typesemiconductor regions PRa and PRb is in contact with the channel layerCH.

More specifically, as illustrated in FIG. 25 , formation of the p-typesemiconductor regions PRa and PRb is started at a higher position thanthat in the first embodiment (FIG. 1 ). The p-type semiconductor regionsPRa and PRb described above can be formed by, for example, adding ashallower ion implantation step to the multi-stage ion implantationstep. In Applied Example 2, the body contact regions BC may be formeddeeply as is the case with Applied Example 1 described above.

Also in the second embodiment, it is possible to achieve the effect ofminiaturizing the semiconductor elements and improving the elementcharacteristics described in the first embodiment. Moreover, since thep-type semiconductor regions PRa and PRb are connected to the sourceregion SR and thus grounded in the second embodiment, it is possible toreduce parasitic capacitance and to improve switching characteristics.

Third Embodiment

In the first embodiment (FIG. 1 ), a step difference is generated as aresult of over-etching between the front surface of the epitaxial layer(source region SR) EP on both sides of the side wall films SW and thefront surface of the epitaxial layer (source region SR) EP covered withthe side wall films SW. However, the configuration in which the stepdifference is eliminated may be adopted.

[Description of Structure]

FIG. 26 is a cross-sectional view illustrating a configuration of asemiconductor device according to the third embodiment. In thesemiconductor device according to the third embodiment, the frontsurface of the epitaxial layer (source region SR) EP on both sides ofthe side wall films SW is located at approximately the same height asthat of the front surface of the epitaxial layer (source region SR) EPcovered with the side wall films SW (see FIG. 34 ), and the stepdifference illustrated in the first embodiment (FIG. 1 ) is notgenerated. The configuration except for these components is the same asthat of the first embodiment (FIG. 1 ), and thus the description thereofis omitted. Furthermore, operation of the semiconductor device(transistor) according to the third embodiment is the same as that inthe first embodiment.

Also in the third embodiment, it is possible to achieve the effect ofminiaturizing the semiconductor elements and improving the elementcharacteristics described in the first embodiment. Moreover, since nostep difference is present on the front surface of the source region SRin the third embodiment unlike the first embodiment, it is possible toreduce the source resistance.

[Description of Manufacturing Method]

Next, a manufacturing method of the semiconductor device according tothe third embodiment will be described with reference to FIGS. 27 to 39, and a configuration of the semiconductor device will be furtherclarified. FIGS. 27 to 38 are cross-sectional views illustrating amanufacturing process of the semiconductor device according to the thirdembodiment.

As illustrated in FIG. 27 , a p-type semiconductor region serving as thechannel layer CH, an n-type semiconductor region serving as the sourceregion SR, and p-type semiconductor regions serving as the body contactregions BC are formed in the epitaxial layer EP on the SiC substrate 1S.These regions can be formed in the same manner as that of the firstembodiment.

Next, as illustrated in FIG. 28 , the polycrystalline silicon film PS isdeposited as a stopper film ST on the epitaxial layer EP so as to have afilm thickness of approximately 100 nm by the CVD or the like.

Then, as illustrated in FIG. 29 , the trench TR that penetrates thestopper film ST, the source region SR, and the channel layer CH to reachthe drift layer DR is formed.

For example, the insulating film IF1 having an opening in the formationregion of the trench TR is formed on the stopper film ST by using aphotolithography technique and an etching technique. Next, the stopperfilm ST, the source region SR, the channel layer CH, and an upperportion of the drift layer DR are etched with using the insulating film(hard mask) IF1 as a mask to form the trench TR.

Then, as illustrated in FIGS. 30 to 32 , the dummy gate DG that isprovided in the trench TR and protrudes upward from the trench TR isformed. First, as illustrated in FIG. 30 , a polycrystalline siliconfilm PS is deposited as a dummy gate material in the trench TR and onthe insulating film IF1 so as to have a film thickness sufficient tofill the trench TR by the CVD or the like. Then, as illustrated in FIG.31 , an upper portion of the polycrystalline silicon film PS is polishedby the CMP or the like until the insulating film IF1 is exposed. Thedummy gate DG is formed in this manner. Next, as illustrated in FIG. 32, the insulating film IF1 is removed by the etching technique. As aresult, the dummy gate DG that is embedded in the trench TR andprotrudes from a front surface of the stopper film ST by a distanceequivalent to the film thickness of the insulating film IF1 can beformed.

Then, as illustrated in FIGS. 33 to 35 , the p-type semiconductorregions (PRa and PRb) are formed in the drift layer DR on both sides ofthe trench TR. First, as illustrated in FIG. 33 , an insulating film(for example, a silicon oxide film) IF2 for forming the side wall filmsSW is formed on the stopper film ST and on the dummy gate DG by usingCVD or the like. Then, the insulating film IF2 is etched back asillustrated in FIG. 34 . In the etch-back step, the insulating film IF2is removed by anisotropic dry etching from a front surface thereof by apredetermined film thickness. This step allows the insulating film IF2to remain like side walls on the side wall portions on both sides of theprotruding portion of the dummy gate DG to form the side wall films SW.

In the third embodiment, when the side wall films SW are formed, thefront surface of the epitaxial layer (source region SR) EP on both sidesof the side wall films SW is not etched even if over-etching isperformed. This is because the stopper film ST exhibiting appropriateetching selectivity with respect to the insulating film IF2 is arrangedon the epitaxial layer EP. Accordingly, the step difference illustratedin the first embodiment (FIG. 1 ) between the front surface of theepitaxial layer (source region SR) EP on both sides of the side wallfilms SW and the front surface of the epitaxial layer (source region SR)EP covered with the side wall films SW is not generated.

Then, as illustrated in FIG. 35 , the p-type semiconductor regions (PRaand PRb) are formed by ion implantation. For example, p-type impuritiessuch as aluminum (Al) or boron (B) are implanted into the drift layer DRwith using the dummy gate DG and the side wall films SW as a mask.During the ion implantation, ion implantation conditions such as ionimplantation energy are adjusted such that each of the p-typesemiconductor regions (PRa and PRb) is located at the position deeperthan the lower surface of the channel layer CH. The above-describedmulti-stage implantation may be used to form the p-type semiconductorregions (PRa and PRb). In this case, the upper surface of each of thep-type semiconductor regions (PRa and PRb) is located at a positionhigher than the bottom surface of the trench TR. Furthermore, the lowersurface of each of the p-type semiconductor regions (PRa and PRb) islocated at a position lower than the bottom surface of the trench TR. Inother words, the trench TR and the p-type semiconductor regions (PRa andPRb) are arranged at overlapping positions in the depth direction (Zdirection).

Also, in this step, the p-type semiconductor regions (PRa and PRb orelectric-field relaxation layers) are formed by ion implantation usingthe dummy gate DG in the trench TR and the side wall films SW formed onboth sides of the dummy gate DG as a mask as described above. Therefore,it is possible to reduce the distance La between the p-typesemiconductor region PRa and the trench TR and the distance Lb betweenthe p-type semiconductor region PRb and the trench TR. Furthermore, thesymmetry of the semiconductor regions with respect to the trench can beenhanced. That is, the distance between the p-type semiconductor regionsPRa and PRb can be reduced, and for example, each of the distance L1 aand the distance L1 b can be made shorter than or equal to the width Wof the trench TR, which is formed to have a width close to theresolution limit.

Then, as illustrated in FIG. 36 , the dummy gate DG and the stopper filmST are removed by using the etching technique. In the above-describedstep, the dummy gate DG and the stopper film ST are both thepolycrystalline silicon film PS, but may be formed of different films.However, the dummy gate DG and the stopper film ST formed of the samefilm can be removed by a single etching process. Furthermore, as a dummygate material and a stopper film material, another material exhibitingappropriate etching selectivity with respect to the insulating film IF2when the side wall films SW are formed may be used. Then, thermaltreatment (activation annealing) is performed to activate the alreadyimplanted impurities.

Next, as illustrated in FIG. 37 , the gate insulating film GI is formed,and the gate electrode GE is further formed. The gate insulating film GIand the gate electrode GE can be formed in the same manner as that ofthe first embodiment.

Then, as illustrated in FIG. 38 , after the interlayer insulating filmIL1 covering the gate electrode GE is formed and the contact holes C1are formed, the source electrode SE is formed. Moreover, the surfaceprotection film PAS is formed to cover the source electrode SE, and thedrain electrode DE is formed on the back surface of the SiC substrate 1S(FIG. 26 ). The interlayer insulating film IL1, the contact holes C1,the surface protection film PAS, and the drain electrode DE can beformed in the same manner as that of the first embodiment.

Fourth Embodiment

In the first embodiment (FIG. 1 ), the p-type semiconductor regions (PRaand PRb or electric-field relaxation layers), which are embedded layers,are provided on both sides of the trench TR below the channel layer CH.However, a p-type semiconductor region (RPt, electric-field relaxationlayer) may be provided also below the trench TR.

[Description of Structure]

FIG. 39 is a cross-sectional view illustrating a configuration of asemiconductor device according to a fourth embodiment. The semiconductordevice according to the fourth embodiment is provided with the p-typesemiconductor region (PRt) below the trench TR in addition to the p-typesemiconductor regions (PRa and PRb) on both sides of the trench TR.

The p-type semiconductor regions PRa and PRt are spaced apart from eachother, and a distance between the p-type semiconductor regions PRa andPRt in plan view is, for example, La. The p-type semiconductor regionsPRb and PRt are spaced apart from each other, and a distance between thep-type semiconductor regions PRb and PRt in plan view is, for example,Lb. In the fourth embodiment, the configuration except for the p-typesemiconductor region PRt is the same as that of the first embodiment(FIG. 1 ), and thus the description thereof is omitted. Furthermore,operation of the semiconductor device (transistor) according to thefourth embodiment is the same as that in the first embodiment.

As described above, in the fourth embodiment, it is possible to achievethe effect of miniaturizing the semiconductor elements and improving theelement characteristics described in the first embodiment. Moreover,since the p-type semiconductor region PRt is provided, theelectric-field relaxation effect can be improved.

[Description of Manufacturing Method]

Next, a manufacturing method of the semiconductor device according tothe fourth embodiment will be described with reference to FIGS. 40 to 43, and a configuration of the semiconductor device will be furtherclarified. FIGS. 40 to 43 are cross-sectional views illustrating amanufacturing process of the semiconductor device according to thefourth embodiment.

As illustrated in FIG. 40 , a p-type semiconductor region serving as thechannel layer CH, an n-type semiconductor region serving as the sourceregion SR, and p-type semiconductor regions serving as the body contactregions BC are formed in the epitaxial layer EP on the SiC substrate 1S.These regions can be formed in the same manner as that of the firstembodiment. Then, the trench TR that penetrates the source region SR andthe channel layer CH to reach the drift layer DR is formed.

For example, the insulating film IF1 having an opening in the formationregion of the trench TR is formed on the stopper film ST by using aphotolithography technique and an etching technique. Next, the sourceregion SR, the channel layer CH, and an upper portion of the drift layerDR are etched with using the insulating film (hard mask) IF1 as a maskto form the trench TR.

Then, as illustrated in FIG. 41 , the p-type semiconductor region PRt isformed at a bottom portion of the trench TR by the ion implantation. Forexample, p-type impurities such as aluminum (Al) or boron (B) areimplanted into the bottom portion of the trench TR with using theinsulating film IF1 as a mask. At this time, multi-stage implantationmay be used to form the p-type semiconductor region PRt.

Then, as illustrated in FIG. 42 and FIG. 43 , the p-type semiconductorregions PRa and PRb are formed. For example, as illustrated in FIG. 42 ,the polycrystalline silicon film PS is deposited as a dummy gatematerial by the CVD or the like so as to have a film thicknesssufficient to fill the trench TR. Then, after an upper portion of thepolycrystalline silicon film PS is polished by the CMP or the like untilthe insulating film IF1 is exposed, the insulating film IF1 is removedby the etching technique. As a result, the dummy gate DG that isembedded in the trench TR and protrudes from a front surface of thestopper film ST by a distance equivalent to the film thickness of theinsulating film IF1 can be formed (FIG. 43 ).

Then, as is the case with the first embodiment, the side wall films SWare formed on side walls of the dummy gate DG, and p-type impurities areimplanted into the drift layer DR with using the dummy gate DG and theside wall films SW as a mask to form the p-type semiconductor regions(PRa and PRb) (FIG. 43 ).

The subsequent steps are similar to those in the first embodiment.

Fifth Embodiment

In a fifth embodiment, a taper T is formed at an end of each of thep-type semiconductor regions PRa and PRb on a side closer to the trenchTR.

[Description of Structure]

FIG. 44 is a cross-sectional view illustrating a configuration of thesemiconductor device according to the fifth embodiment. As illustratedin FIG. 44 , in the fifth embodiment, the taper (tapered portion) T isprovided at an end of the p-type semiconductor region PRa on a sidecloser to the trench TR such that a distance (L3 a) between a lowerportion of the p-type semiconductor region PRa and the trench TR is madelarger than a distance (La) between an upper portion of the p-typesemiconductor region PRa and the trench TR. Furthermore, the taper T isprovided at an end of the p-type semiconductor region PRb on a sidecloser to the trench TR such that a distance (L3 b) between a lowerportion of the p-type semiconductor region PRb and the trench TR is madelarger than a distance (Lb) between an upper portion of the p-typesemiconductor region PRb and the trench TR.

In the fifth embodiment, the configuration except for the ends of thep-type semiconductor regions PRa and PRb on the side closer to thetrench TR is the same as that of the first embodiment (FIG. 1 ), andthus the description thereof is omitted. Furthermore, operation of thesemiconductor device (transistor) according to the fifth embodiment isthe same as that in the first embodiment.

As described above, in the fifth embodiment, it is possible to achievethe effect of miniaturizing the semiconductor elements and improving theelement characteristics described in the first embodiment. Moreover,since the current path can be widened by increasing the distances L3 aand L3 b, it is possible to reduce the on-resistance.

[Description of Manufacturing Method]

Next, a manufacturing method of the semiconductor device according tothe fifth embodiment will be described with reference to FIGS. 45 to 53and a configuration of the semiconductor device will be furtherclarified. FIGS. 45 to 53 are cross-sectional views illustrating amanufacturing process of the semiconductor device according to the fifthembodiment.

As illustrated in FIG. 45 , a p-type semiconductor region serving as thechannel layer CH, an n-type semiconductor region serving as the sourceregion SR, and p-type semiconductor regions serving as the body contactregions BC are formed in the epitaxial layer EP on the SiC substrate 1S.These regions can be formed in the same manner as that of the firstembodiment. Then, the trench TR that penetrates the source region SR andthe channel layer CH to reach the drift layer DR is formed.

For example, the insulating film IF1 having an opening in the formationregion of the trench TR is formed on the epitaxial layer EP by using aphotolithography technique and an etching technique. Next, the sourceregion SR, the channel layer CH, and an upper portion of the drift layerDR are etched with using the insulating film (hard mask) IF1 as a maskto form the trench TR. Then, the dummy gate DG embedded in the trench isformed, and the insulating film IF1 is removed by using the etchingtechnique (FIG. 46 ).

Next, as illustrated in FIG. 47 , an insulating film (for example, asilicon oxide film) IF21 is formed on the epitaxial layer (source regionSR) EP and the dummy gate DG. In the fifth embodiment, the high densityplasma CVD is used to form the insulating film (for example, a siliconoxide film) IF21 so as to have a film thickness of approximately 1 to 4The high density plasma CVD refers to a film formation method ofdepositing an insulating film under a high density plasma atmosphere. Inthe high density plasma CVD, by depositing an insulating film whileetching the insulating film, the film can be accurately embedded even infine gaps, and the film with good flatness can be obtained. The highdensity plasma CVD as described above enables to form a protrudingportion with a substantially triangular cross section on the dummy gateDG. Side walls of the protruding portion are tapered at an angle(inclination angle θ) of 45°. Note that a height of the protrudingportion can be controlled based on the film thickness of the insulatingfilm IF21. Then, as illustrated in FIG. 48 , the insulating film IF21 isetched back, that is, removed by anisotropic dry etching by apredetermined film thickness from a front surface thereof, so thatinsulating films TL with side walls inclined at an angle of 45° areformed on both sides of the dummy gate DG. In other words, theinsulating films TL with tapered side surfaces are formed on the sidewalls of the dummy gate DG. The position of each of the insulating filmsTL can be controlled based on the film thickness of the insulating filmIF21.

Then, as illustrated in FIG. 49 , an insulating film (for example, asilicon oxide film) IF2 for forming the side wall films SW is formed onthe epitaxial layer (source region SR) EP, the insulating film TL, andthe dummy gate DG by the CVD or the like. Then, the insulating film IF2is etched back as illustrated in FIG. 50 . In the etch-back step, theinsulating film IF2 is removed by a predetermined film thickness fromthe front surface thereof by the anisotropic dry etching. By this step,the insulating film IF2 shaped like side walls remains on the insulatingfilm TL on both sides of the protruding portion of the dummy gate DGalong the side walls of the dummy gate DG, thereby forming the side wallfilms SW. In this case, the front surface of portions of the epitaxiallayer (source region SR) EP on both sides of the insulating film TL maybe slightly etched by over-etching.

Then, as illustrated in FIG. 51 , the p-type semiconductor regions (PRaand PRb) are formed by using ion implantation. For example, p-typeimpurities such as aluminum (Al) or boron (B) are implanted into thedrift layer DR with using the dummy gate DG, the insulating film TL, andthe side wall films SW as a mask. In the ion implantation, the p-typesemiconductor regions (PRa and PRb) are not formed below the side wallfilms SW, and the taper T is formed at each of the ends of the p-typesemiconductor regions (PRa and PRb) by reflecting the side walls of theinsulating film TL having an inclination angle of 45°. In other words,the distance between each of the p-type semiconductor regions PRa andPRb and the trench TR gradually increases in the depth direction (La→L3a, Lb→L3 b). Note that the shortest distance between each of the p-typesemiconductor regions PRa and PRb and the trench TR is shorter than orequal to the width of the trench TR.

Next, as illustrated in FIG. 52 , the dummy gate DG and others areremoved by the etching technique. Then, as illustrated in FIG. 53 ,after the gate insulating film GI is formed and the gate electrode GE isfurther formed, the interlayer insulating film IL1 covering the gateelectrode GE is formed, and the contact holes C1 are formed. These canbe formed in the same manner as the first embodiment. Then, the sourceelectrode SE is formed, and the surface protection film PAS is formed soas to cover the source electrode SE and others (FIG. 54 ). Thereafter,the drain electrode DE is formed on the back surface of the SiCsubstrate 1S (FIG. 44 ). The surface protection film PAS and the drainelectrode DE can be formed in the same manner as the first embodiment.

Sixth Embodiment

In a sixth embodiment, contact holes are formed in formation regions ofthe body contact regions BC, and the body contact regions BC areprovided at the bottom portions of the corresponding contact holes.

[Description of Structure]

FIG. 54 is a cross-sectional view illustrating a configuration of asemiconductor device according to the sixth embodiment. As illustratedin FIG. 54 , in the sixth embodiment, contact holes C21 are provided inthe formation regions of the body contact regions BC, and the bodycontact regions BC are provided at bottom portions of the correspondingcontact holes C21. Each of the contact holes C21 is a hole penetratingthe source region SR to reach the channel layer CH. Also, the contacthole C21 is arranged below the contact hole C1. With respect to thecontact holes (C1 and C21) mentioned here, a wider portion of the set ofthe contact holes corresponds to the contact hole C1, and a narrowerportion of the set of the contact holes (C1 and C21) located below thecontact hole C1 corresponds to the contact hole C21.

In the sixth embodiment, the configuration except for the contact holesC21 and the corresponding body contact regions BC at the bottom portionsthereof is substantially the same as that of the first embodiment (FIG.1 ), and thus the description thereof is omitted. Furthermore, operationof the semiconductor device (transistor) according to the sixthembodiment is the same as that in the first embodiment.

Also in the sixth embodiment, it is possible to achieve the effect ofminiaturizing the semiconductor elements and improving the elementcharacteristics described in the first embodiment.

[Description of Manufacturing Method]

Next, a manufacturing method of the semiconductor device according tothe sixth embodiment will be described with reference to FIGS. 55 to 65and a configuration of the semiconductor device will be furtherclarified. FIGS. 55 to 65 are cross-sectional views illustrating amanufacturing process of the semiconductor device according to the sixthembodiment.

As illustrated in FIG. 55 , the SiC substrate 1S provided with theepitaxial layer EP is prepared, and a p-type semiconductor regionserving as the channel layer CH and an n-type semiconductor regionserving as the source region SR are formed by ion implantation asillustrated in FIG. 56 . These can be formed in the same manner as thefirst embodiment.

Next, as is the case with the first embodiment, the trench TR thatpenetrates the source region SR and the channel layer CH to reach thedrift layer DR is formed (FIG. 57 ). Then, as is the case with the firstembodiment, the dummy gate DG that is provided in the trench TR andprotrudes upward from the trench TR is formed (FIG. 58 ).

Next, as is the case with the first embodiment, the side wall films SWare formed on the side wall portions on both sides of the protrudingportion of the dummy gate DG, and p-type impurities are ion-implantedwith using the dummy gate DG and the side wall films SW as a mask toform the p-type semiconductor regions PRa and PRb (FIG. 59 ). Then, thedummy gate DG and the like are removed by the etching technique (FIG. 60).

Next, as illustrated in FIG. 61 , the contact holes C21 are formed inthe source regions SR on both sides of the trench TR. For example, hardmask (not illustrated in the drawings) having openings in formationregions of the contact holes C21 is formed on the source region SR bythe photolithography technique and the etching technique. Then, thesource region SR and the upper portion of the channel layer CH areetched with using the hard mask (not illustrated in the drawings) as amask to form the contact holes C21. The channel layer CH is exposed in abottom surface of each of the contact holes C21.

Next, as illustrated in FIG. 62 and FIG. 63 , the body contact regionsBC are formed below bottom surfaces of the contact holes C21, and thegate insulating film GI is further formed on the source region SRincluding the inside of the trench TR and each of the contact holes C21.

For example, the body contact regions BC are formed by ion-implantingp-type impurities into the channel layer CH exposed in the bottomsurface of each of the contact holes C21 with using the hard mask (notillustrated in the drawings) as a mask (FIG. 62 ). The concentration ofthe p-type impurities in the body contact regions BC is higher than thatof the p-type impurities in the channel layer CH. The, the hard mask(not illustrated in the drawings) is removed.

Next, for example, a silicon oxide film serving as the gate insulatingfilm GI is formed by the ALD or the like on the source region SRincluding the inside of the trench TR and each of the contact holes 21(FIG. 63 ).

Next, as illustrated in FIG. 64 , the gate electrode GE and theinterlayer insulating film IL1 covering the gate electrode GE areformed, and the contact holes C1 are formed.

For example, as is the case with the first embodiment, a silicon oxidefilm is formed as the interlayer insulating film IL1 on the gateelectrode GE by the CVD. Then, a photoresist film (not illustrated inthe drawings) having openings above each of the body contact regions BCand portions of the source region SR on both sides of the body contactregions BC is formed on the interlayer insulating film IL1. Then, theinterlayer insulating film IL1 is etched with using the photoresist filmas a mask, thereby forming the contact holes C1. The contact holes C21are located below the respective contact holes C1. Each of the bodycontact regions BC and the portions of the source region SR on bothsides of the body contact region BC are exposed below the set of thecontact holes (C1 and C21).

Next, as illustrated in FIG. 65 , the source electrode SE is formed. Thesource electrode SE and the like may be formed after a silicide film isformed on the bottom surface of the set of the contact holes C21 and C1.In a case where the bottom surface of each the contact holes isroughened by etching at the time of forming the contact holes, thesilicide grows well. Thereafter, the surface protection film PAS isformed so as to cover the source electrode SE and the like, and thedrain electrode DE is formed on the back surface of the SiC substrate 1S(FIG. 54 ). The source electrode SE, the surface protection film PAS,and the drain electrode DE can be formed in the same manner as the firstembodiment.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

For example, any of the embodiments and the applied examples may becombined together. For example, one of Applied Examples 1 and 2 of thesecond embodiment may be applied to any of the third to sixthembodiments. Alternatively, the third embodiment may be applied to thefourth embodiment or the like. In addition, the fourth embodiment may beapplied to the fifth embodiment or the like. Furthermore, the n-typetransistor may be replaced with a p-type transistor. Also, the epitaxiallayer EP may be omitted, and the channel layer CH, the source region SR,and the like may be formed in the SiC substrate 1S.

Furthermore, in the above-described embodiments, the trench gate typepower transistor made of SiC has been described by way of example.However, the configurations of the above-described embodiments may beapplied to a trench gate type power transistor made of Si. However, asdescribed above, although a high breakdown voltage of SiC itself can beensured because SiC has a wider bandgap than silicon (Si), it isimportant to enhance the breakdown voltage in the components made ofother materials (gate insulating film and the like). Thus, theabove-described embodiments are more effectively applied to a trenchgate type power transistor made of SiC.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate having a first main surface and a second mainsurface opposite to the first main surface; a drift layer of a firstconductivity type formed over the semiconductor substrate; a channellayer of a second conductivity type opposite to the first conductivitytype formed on the drift layer; a source region of the firstconductivity type formed on the channel layer; a trench penetrating thesource region and the channel layer to reach the drift layer; a gateelectrode embedded in the trench via a gate insulating film; a firstsemiconductor region of the second conductivity type formed in the driftlayer such that the first semiconductor region contacts a bottom surfaceof the trench; a second semiconductor region of the second conductivitytype formed in the drift layer at a first side of the firstsemiconductor region in plan view; and a third semiconductor region ofthe second conductivity type formed in the drift layer at a second sideopposite to the first side of the first semiconductor region in planview, wherein the second semiconductor region and the thirdsemiconductor region are separate apart from the first semiconductorregion.
 2. The semiconductor device according to claim 1, wherein thefirst semiconductor region and the bottom surface of the trench areoverlapped in plan view.
 3. The semiconductor device according to claim1, wherein a first distance between the second semiconductor region andthe trench in plan view and a second distance between the thirdsemiconductor region and the trench in plan view are approximately same.4. The semiconductor device according to claim 1, wherein the secondsemiconductor region and the third semiconductor region are separateapart from the channel layer.
 5. The semiconductor device according toclaim 1, further comprising: a body contact region of the secondconductivity type formed in the source region and the channel layer,wherein one end of the source region contacts the trench, and other endof the source region contacts the body contact region.
 6. Thesemiconductor device according to claim 5, wherein an impurityconcentration of the body contact region is higher than an impurityconcentration of the channel layer.
 7. The semiconductor deviceaccording to claim 1, wherein the drift layer, the channel layer, thesource region, the first semiconductor region, the second semiconductorregion and the third semiconductor region are configured by SiC.
 8. Thesemiconductor device according to claim 1, further comprising: aninterlayer insulating film formed on the gate electrode; and a contacthole formed in the interlayer insulating film; a source electrode formedon the interlayer insulating film and in the contact hole, a drainelectrode formed on the second main surface, wherein the gate electrode,the source electrode and the drain electrode configure a transistor.